The array substrate is widely used in the field of flat panel display technology as a component for controlling switches and driving peripheral circuits. In the commonly used array substrate, since the pattern between the layers cannot be completely aligned and the overlapping area between the gate and the source and the drain may be partially generated, a parasitic capacitance is generated, and the generation of the parasitic capacitance to the display panel is unacceptable, which will seriously affect the performance of the display panel. Therefore, it is urgent to find a new type of array substrate structure to prevent the generation of parasitic capacitance and improve the performance of the display panel.